1. Field of the Invention
The invention relates to a serial in-circuit emulator architecture, and in particular to a serial in-circuit emulator which can be readily integrated with CPUs without affecting the operating speed thereof.
2. Description of Related Art
Generally, to debug software programs, a conventional serial in-circuit emulator (ICE) can pause the operation of a CPU to check, access or modify the status of the CPU. Furthermore, this serial in-circuit emulator can also read/write current data from/to an external memory or other I/O devices, or modify these data. Besides, the serial in-circuit emulator can also change the process of running software programs from a continuously-executing mode into a step-by-step executing mode so as to monitoring the status changing step-by-step. The conventional serial in-circuit emulator is mostly based on "IEEE Standard 1149.1 (JTAG)." However, while a general CPU is integrated with such conventional serial in-circuit emulator or a serial in-circuit interface, several disadvantages are encountered:
(1) A scan chain must be added on original I/O pins and specific internal registers. That is, multiplexers and scan-type flip-flops should be added on I/O pins or specific internal registers;
(2) Since a serial in-circuit emulator need to be integrated with different types of CPUs, the serial in-circuit emulator must be appropriately modified, resulting in increasing the development time for CPUs;
(3) Due to increasing the functions of the serial in-circuit emulator, the number of I/O pins of original CPU should be increased about 4-5 pins; and
(4) Although there may be several very simple serial in-circuit emulators, they can not provide all necessary functions that general serial in-circuit emulators should have. For example, some specific status inside the CPUs can not be accessed, or a hardware single-stepping may not be supported.